1. Field of the Invention
The present invention relates to an uninterruptible power supply (UPS), especially to a controlling method of a battery mode of an UPS for an active power factor corrected load having a hold-up time circuit.
2. Description of Related Art
The Computer Business Equipment Manufacturer's Association creates the CBEMA guideline. The guideline specifies that all computer business equipment has to provide a hold-up time of at least 8ms after the power source is terminated.
The power supply, for example, has a hold-up time circuit, that is, the amount of time that a power supply can continue to supply the load after input power is terminated. The duration of a BLACKOUT or TRANSFER TIME is the time that a power supply can accept without any disturbance of the output. Therefore, a computer equipment using the power supply with a hold-up time circuit has enough time to orderly terminate the operations of a data-processing procedure. In addition, if the AC power source is supplied to a switching power supply through a UPS, the hold-up time is used to switch over to the UPS operation after the AC power is terminated.
The switching power supply is one kind of power supply and uses an active power factor corrected (PFC) circuit to increase power translation efficiency up to 98%. Therefore, the computer equipment generally uses the active PFC switching power supply to save power. With reference to FIG. 4, an active PFC switching power supply (30) has a front end rectifier (31), a bulk capacitor (CBULK) and a DC to DC converter (32). The front end rectifier (31) has a full bridge rectifier (BD) and an active PFC circuit. The full bridge rectifier (BD) is connected to an external AC power source (AC/IN) and then rectifies the AC power source to a DC power. The bulk capacitor (CBULK) is connected to an output of the PFC circuit, so the bulk capacitor (CBULK) is charged by the DC power from the PFC circuit. In general, the bulk capacitor (CBULK) usually uses about 100 uF to store about hundred voltages of the DC power therein. The bulk capacitor (CBULK) discharges a short term DC power for the DC to DC converter (32). Therefore, the DC to DC converter (32) continually outputs the DC power source to a computer equipment for a few milliseconds after the external AC power source (AC/IN) is terminated. With further reference to FIGS. 5A and 5B, when the AC power source is terminated, a voltage of the bulk capacitor (CBULK) is gradually decreased. Once the voltage of the bulk capacitor is lower than a low threshold voltage (VBL), the DC to DC converter does not operate and the active PFC switching power supply (30) does not supply DC power to the computer equipment anymore. Therefore, the hold up time (TH) is defined to a term between the high voltage (VBH) and the low threshold voltage (VBL).
In general, the computer equipment requires a UPS to provide an emergency power when the AC power source is terminated. Therefore, the UPS has a line mode and a battery mode. The line mode of the UPS is operated during the AC power source is normal and the battery mode of the UPS is operated when the line mode is fails. With reference to FIG. 6, the UPS (40) has an inverter (41), a transformer (42), a battery charger (43) and a battery set (44). Transformer (42) is connected between the AC power source (AC/IN), the active PFC switching power supply (30), the inverter (41) and the battery charger (43). When the AC power source (AC/IN) is normal, the AC power source (AC/IN) is connected to the switching power supply (30) and the battery set (44) is charged through the battery charger (43) to store DC power. If the AC power source is abnormal or terminated, the line mode fails and the inverter (41) converts the DC power of the battery set (44) to a square wave.
The inverter (41) has a controller (411) and two power transistors (Q1, Q2) connected to the transformer (42) in serial. The controller (411) is connected to controlling terminals (G1, G2) of the power transistors (Q1, Q2), so as to turn on or turn off the two power transistors (Q1, Q2). With further reference to FIG. 7B and 7C, the controller (411) outputs two PWM signals (VG1, VG2) to the corresponding power transistors (Q1, Q2) to alternately switch the two power transistors (Q1, Q2). With further reference to FIG. 7A, the UPS (40) outputs the square wave (VO) to the switching power supply (30). However, an OFF time (T12) between two adjacent pulses (P1, P2) in a period (T) may be longer than the hold-up time (TH) of the active PFC switching power supply (30). The UPS (30) does not supply emergency power according to the pulse (P2) to the active PFC switching power supply (30) during the hold-up time (TH), so the voltage of the bulk capacitor (CBULK) is lower than the low threshold voltage (VBL). Therefore, the DC to DC converter shuts down and does not output the DC power source to the computer equipment even the battery mode of the UPS is still working.
To overcome the shortcomings, the present invention provides a controlling method of the battery mode of the UPS to mitigate or obviate the aforementioned problems.